1. Field of the Invention
The present invention relates to a method and apparatus for extracting a model parameter for a circuit simulation for a semiconductor memory element. More particularly, the present invention relates to a method of calculating a resistance value of an offset region in a semiconductor memory element having a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed just below the gate electrode via the gate insulating film, two diffusion regions formed on the both sides of the channel region, a memory function element formed on one side or both sides of the gate electrode and having a charge retaining function, and an offset region positioned below the memory function element and isolating the channel region and the diffusion region from each other, and constructed so that the diffusion region formed on the side where the memory function element exists and the channel region are isolated from each other by the offset region and the resistance value of the offset region changes according to the amount of charges or a polarization state of charges accumulated in said memory function element, and relates to a method and apparatus of extracting a model parameter of a semiconductor memory element by using a model formula precisely expressing a calculated resistance value.
2. Description of the Related Art
As a conventional nonvolatile semiconductor memory element generally spread, there is a flash memory constructed by a transistor having a floating-gate structure. In the flash memory, as shown in FIG. 31, a floating gate 902, an insulating film 907, and a word line (control gate) 903 are formed in this order over a semiconductor substrate 901 via a gate insulating film. On both sides of the floating gate 902, a source line 904 and a bit line 905 are formed by a diffusion region, thereby constructing a memory cell. A device isolation region 906 is formed around the memory cell (see, for example, JP-A 05-304277 (1993)).
The memory cell in the flash memory stores information in accordance with an amount of charges in the floating gate 902. In a memory cell array constructed by arranging memory cells, by selecting a specific word line and a specific bit line and applying a predetermined voltage, an operation of rewriting/reading a desired memory cell can be performed. In such a flash memory, when the amount of charges in the floating gate changes, a drain current (Ids)-gate voltage (Vgs) characteristic as shown in FIG. 32 is displayed. When the amount of negative charges in the floating gate increases, the threshold increases and the Ids-Vgs curve shifts almost in parallel to the Vgs increasing direction.
In such a flash memory, however, the insulating film 907 which separates the floating gate 902 and the word line 903 is necessary from the viewpoint of functions, and in order to prevent leakage of charges from the floating gate 902, it is difficult to reduce the thickness of the gate insulating film. Consequently, it is difficult to effectively reduce the thickness of the insulating film 907 and the gate insulating film, and it disturbs reduction in the size of the memory cell.
There is a move afoot to provide a novel semiconductor memory element of which size is easily reduced by employing a semiconductor memory element disclosed in International Publication WO 03/044868 as a semiconductor memory element constructed so that the resistance value of an offset region positioned below a memory function element changes according to an amount of charges or a polarization state of charges accumulated in the memory function element formed on one side or both sides of a gate electrode.
There is also a semiconductor memory element disclosed in JP-A 05-81072 (1993) which has a structure and forms an offset region similar to those of the semiconductor memory element disclosed in International Publication WO 03/044868.
As described above, a semiconductor memory element constructed so that the resistance value of the offset region positioned below the memory function element changes according to an amount of charges or a polarization state of charges accumulated in the memory function element formed on one side or both sides of the gate electrode has, first, a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions formed on both sides of the channel region and having a conduction type opposite to that of the channel region, and memory function elements formed on both sides of the gate electrode and having a charge retaining function. The memory function of the memory function element and a transistor operating function of the gate insulating film are separated from each other. Therefore, while maintaining the sufficient memory function, the gate insulating film can be thinned and it is easy to suppress a short channel effect. Further, as compared with an EEPROM, the value of current flowing between diffusion regions largely changes by rewriting. Thus, it becomes easier to discriminate between the programming state and the erasing state of the semiconductor memory element.
Further, the semiconductor memory element of the present invention can be formed by a process which is very compatible with a normal transistor forming process on the basis of the configuration. Therefore, as compared with the case of using a conventional flash memory as a nonvolatile memory device together with a normal transistor, the number of masks and the number of processes can be dramatically reduced. Consequently, the yield of a chip on which both the semiconductor memory element and a normal transistor circuit are formed can be improved. Due to this, the manufacturing cost is reduced and, accordingly, reliability improves.
To perform a circuit simulation on a circuit including the semiconductor memory element having the excellent characteristics, a set of model parameters of a model for a circuit simulation expressing electric characteristics of the semiconductor memory element is necessary. The semiconductor memory element is different from a general IGFET (insulated gate field-effect transistor, a MOSFET being a kind of the IGFET) with respect to the points that an offset region is provided on both sides or one side of the channel region disposed just below the gate electrode and a memory function element is provided on both sides or one side of the gate electrode.
However, it is difficult to precisely extract a model parameter with respect to an electrostatic characteristic of the semiconductor memory element by using a normal IGFET model (for example, BSIM3 developed mainly by University of California, Berkley, U.S.A.) as a conventional technique by the differences for the following reason. The resistance value of resistance of the offset region existing on both sides or one side of the channel region just below the gate electrode changes according to an amount of charges or a polarization state of charges accumulated in the memory function element positioned on both sides or one side of the gate electrode, and the gate voltage dependency, substrate voltage dependency, and drain voltage dependency of the offset region are largely different from those of the channel region just below the gate electrode. There is a problem such that, in particular, when the memory function element on one side or both sides is in a programming state, it is impossible to extract a model parameter with high precision.
Further, at the time of extracting a model parameter with respect to an electrostatic characteristic of the semiconductor memory element, it is very important to obtain, not channel resistance of the offset and channel regions in a lump, but the resistance of the channel region just below the gate electrode and the resistance of the offset region on both sides or one side separately and to accurately grasp the state (erase or program) of the memory function element and an offset resistance value under voltage conditions of the each region (the gate electrode, semiconductor layer, and diffused region).
However, the offset region is a very small region positioned below the memory function element and it is actually impossible to directly connect an electrode to the offset region. Consequently, the actual condition is that it is difficult to directly measure the resistance of the offset region, and a characteristic evaluating method of precisely obtaining the resistance value of the offset region and a model formula and a model parameter for precisely expressing the resistance value of the offset region obtained by the characteristic evaluation do not exist.